Accession Number : ADA294842
Title : Bit-Level Analysis of an SRT Divider Circuit.
Descriptive Note : Research rept.,
Corporate Author : CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE
Personal Author(s) : Bryant, Randal E.
PDF Url : ADA294842
Report Date : 18 APR 1995
Pagination or Media Count : 11
Abstract : It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could have used BDDs to detect erroneous table entries in the Pentium floating point divider. Going beyond verification, we show that bit-level analysis can be used to generate a correct version of the table.
Descriptors : *CIRCUIT TESTERS, *CIRCUIT ANALYSIS, ALGORITHMS, VERIFICATION, SIZES(DIMENSIONS), WORDS(LANGUAGE), CIRCUITS, ARITHMETIC, FLOATING POINT OPERATION, SEPARATORS.
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE