Accession Number : ADA298363
Title : Automatic Layout of Integrated-Optics Time-of-Flight Circuits.
Descriptive Note : Doctoral thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH
Personal Author(s) : Kennett-Fogg, Ruth D.
PDF Url : ADA298363
Report Date : 19 APR 1995
Pagination or Media Count : 146
Abstract : This work describes the architecture and algorithms used in the computer aided design tool developed for the automatic layout of integrated optic, time of flight circuit designs. This is similar to the layout of electronic VLSI circuits, where total wire length and chip area minimization are the major goals. Likewise, total wire length and chip area minimization are also the goals in the layout of time of flight circuits. However, there are two major differences between the layout of time of flight circuits and VLSI circuits. First, the interconnection lengths of time of flight designs are exactly specified in order to achieve the necessary delays for signal synchronization. Secondly, the switching elements are 120 times longer than they are wide. This highly astigmatic aspect ratio causes severe constraints on how and where the switches are placed. The assumed development of integrated corner turning mirrors allows the use of a parallel, row based device placement architecture and a rectangular, fixed grid track system for the connecting paths. The layout process proceeds in two steps. The first step involves the use of a partial circuit graph representation to place the elements in rows, oriented in the direction of the signal flow. After iterative improvement of the placement, the second step proceeds with the routing of the connecting paths. The main problem in the automatic layout of time of flight circuits is achieving the correct path lengths without overlapping previously routed paths. This problem is solved by taking advantage of a certain degree of variability present in each path, allowing the use of simple heuristics to circumvent previously routed paths.
Descriptors : *COMPUTER ARCHITECTURE, *CIRCUIT INTERCONNECTIONS, *OPTICAL CIRCUITS, ALGORITHMS, MIRRORS, INTEGRATED SYSTEMS, COMPUTER AIDED DESIGN, GRIDS, PATHS, THESES, VERY LARGE SCALE INTEGRATION, CHIPS(ELECTRONICS), VARIATIONS, HEURISTIC METHODS, SYNCHRONIZATION(ELECTRONICS), OPTICAL SWITCHING, ASPECT RATIO, TIME STUDIES, CORNER REFLECTORS.
Subject Categories : Electrooptical and Optoelectronic Devices
Distribution Statement : APPROVED FOR PUBLIC RELEASE