Accession Number : ADA299750

Title :   Quarterly Progress Report Number 5 for Contract N00014-93-C-0213 (Formal Systems Design and Development, Inc.).

Descriptive Note : Quarterly rept.,

Corporate Author : FORMAL SYSTEMS DESIGN AND DEVELOPMENT INC AUBURN AL

Personal Author(s) : Goldsmith, Michael

PDF Url : ADA299750

Report Date : 25 APR 1995

Pagination or Media Count : 122

Abstract : This Document summarizes the progress to date in the Office of Naval Research SBIR Project N00014-93-C-0213 Embedded Transputer-based System Design and indicates the expected direction of the Research and Development in the following periods. Overview The level of effort expended was broadly on track during this period both at Formal Systems and at the Charles Stark Draper Laboratory (Draper) and Formal Systems (Europe) Ltd. Most of the slippage against plan reported last quarter had indeed been made up by the end of January, although actual delivery of reports was not achieved at that time. There have again been staff resource difficulties in the first quarter of 1995, with the result that some slippage of Q6 and Q7 deliverables is anticipated. The original schedule had considerable slack in the activities planned for Q8, to allow for just such an eventuality, so this should not impact the scope of the work completed within the project. The main areas of activity and achievement during this period were: Continued experimentation with FDR 2, in parallel with its continued development by Formal Systems (Europe) Ltd, leading to appraisal and feedback into the design. Distillation of this experience into requirements for translation and interface tools, both for increasing the facility of expression of real-time specifications, and for increasing the range of implementation notations from which behaviors amenable to analysis can be (semi-)automatically abstracted. Discussion with Draper and consequent revision of the models of scheduling and architecture of the Transputer Fault-Tolerant Processor node. Acquisition of timing requirements for the demonstrator scheduler, based on potential application systems.

Descriptors :   *SYSTEMS ENGINEERING, *SUPERCOMPUTERS, REQUIREMENTS, DELIVERY, ACQUISITION, MODELS, MICROPROCESSORS, REAL TIME, SPECIFICATIONS, TOOLS, INTERFACES, REPORTS, CHIPS(ELECTRONICS), NODES, SCHEDULING, EMBEDDING, ROUTING, FAULT TOLERANCE, FAULT TOLERANT COMPUTING, FAULTS, TIME STUDIES.

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE