Accession Number : ADA301446
Title : Simulation and Analysis of Predictive Read Cache Performance.
Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Personal Author(s) : Miller, Robert W.
PDF Url : ADA301446
Report Date : JUN 1995
Pagination or Media Count : 56
Abstract : Efforts to speed up the memory hierarchy have failed to keep up with the rapid increase in microprocessor performance. The use of first-level and second-level caches has become common in an effort to minimize this speed discrepancy. One potential method to overcome the speed problem while using much less hardware than a second-level cache, is the predictive read cache. This thesis continues previous efforts in designing and optimizing the predictive read cache. It develops a method to simulate the performance of a memory hierarchy containing a predictive read cache and uses these simulations to determine the most effective architecture of the cache. Using trace data from an Intel 486 processor running the SPEC benchmarks, the simulations demonstrate that a small predictive read cache can give a performance improvement equivalent to a much larger second-level cache. This makes the predictive read cache ideal for systems that are power or chip area limited.
Descriptors : *MICROPROCESSORS, *COMPUTER ARCHITECTURE, *RANDOM ACCESS COMPUTER STORAGE, ALGORITHMS, COMPUTERIZED SIMULATION, OPTIMIZATION, DATA MANAGEMENT, COMPUTER AIDED DESIGN, PREDICTIONS, COMPUTER LOGIC, COMPUTER PROGRAMMING, THESES, INPUT OUTPUT PROCESSING, CHIPS(ELECTRONICS), READ WRITE MEMORIES, ACCESS TIME, SYSTEMS ANALYSIS, HIERARCHIES, BUFFER STORAGE, BYTE FUNCTIONAL MODULES.
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE