Accession Number : ADA303421
Title : Synthesis of Timing-Constrained VLSI Systems.
Descriptive Note : Final rept. 1 Jul 91-14 Oct 94,
Corporate Author : WASHINGTON UNIV SEATTLE NORTHWEST LAB FOR INTEGRATED SYSTEMS
Personal Author(s) : Borriello, Gaetano ; Burns, Steven M. ; Ebeling, Carl ; Snyder, Lawrence
PDF Url : ADA303421
Report Date : 28 NOV 1995
Pagination or Media Count : 27
Abstract : Our research investigated the problem of synthesizing timing-constrained systems, with an emphasis on real-time control circuits and communication-intensive systems. Solving the general problem of synthesizing timing-constrained systems requires solutions to subproblems along a broad front from high-level specification to circuit design and implementation. The specific subproblems we investigated were (1) timing specification, analysis and verification, (2) high-performance clocking methodologies, (3) synthesis of reactive embedded systems, and (4) FPGA architectures and design tools for high-performance circuits and interfaces. (AN)
Descriptors : *VERY LARGE SCALE INTEGRATION, MATHEMATICAL MODELS, ALGORITHMS, SIGNAL PROCESSING, SOFTWARE ENGINEERING, OPTIMIZATION, COMPUTER AIDED DESIGN, COMPUTER COMMUNICATIONS, VERIFICATION, TIME DEPENDENCE, ASYNCHRONOUS SYSTEMS, MICROPROCESSORS, REAL TIME, SPECIFICATIONS, INPUT OUTPUT PROCESSING, GATES(CIRCUITS), CHIPS(ELECTRONICS), CONCURRENT ENGINEERING, CIRCUIT INTERCONNECTIONS, MULTIPROCESSORS, SYNCHRONIZATION(ELECTRONICS), LOGIC CIRCUITS, SYSTEMS ANALYSIS, CIRCUIT ANALYSIS.
Subject Categories : Electrical and Electronic Equipment
Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE