Accession Number : ADA305822
Title : Design Techniques for the Prevention of Radiation-Induced Latch-Up in Bulk CMOS Processes.
Descriptive Note : Master's thesis,
Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Personal Author(s) : Madsen, Anne
PDF Url : ADA305822
Report Date : SEP 1995
Pagination or Media Count : 87
Abstract : Design and layout techniques are described for preventing radiation-induced latch-up in CMOS VLSI ICs using non-radiation hardened bulk CMOS processes. Such ICs are suitable for use in satellites and other systems where proper operation in a radiation environment is critical in the short term, but where long-term survivability is of less importance. Basic radiation effects are discussed, emphasizing areas where bulk CMOS processes are most susceptible. Two custom CMOS VLSI ICs are designed to demonstrate the described techniques. Test plans are developed for testing and evaluating the described ICs using the investigative techniques. (MM)
Descriptors : *RADIATION PROTECTION, *EXTRATERRESTRIAL RADIATION, COMPUTER PROGRAMS, ANNEALING, SPACE ENVIRONMENTS, SURVIVABILITY, THESES, VERY LARGE SCALE INTEGRATION, CHIPS(ELECTRONICS), INTEGRATED CIRCUITS, TRAPPING(CHARGED PARTICLES), ARTIFICIAL SATELLITES, DOPING, GOLD, COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, IONIZING RADIATION, RADIATION DOSAGE, RADIATION HARDENING, RADIATION EFFECTS, RADIATION SHIELDING, COSMIC RAYS.
Subject Categories : Astrophysics
Electrical and Electronic Equipment
Nuclear Physics & Elementary Particle Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE