Accession Number : ADA305842
Title : A Pipelined Vector Processor and Memory Architecture for Cyclostationary Processing.
Descriptive Note : Doctoral thesis,
Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA
Personal Author(s) : Bernstein, Raymond F., Jr
PDF Url : ADA305842
Report Date : DEC 1995
Pagination or Media Count : 276
Abstract : This work describes a scaleable, high performance, pipelined, vector processor architecture. Special emphasis is placed on performing fast Fourier transforms with mixed-radix butterfly operations. The initial motivation for the achitecture was the computation of cyclostationary algorithms. However, the resulting architecture is capable of general purpose vector processing as well. A major factor affecting the performance of the architecture is the memory system design. The use of pipelining techniques, coupled with vector processing, places a substantial burden on the memory system performance. The memory design is based on an interleaved memory philosophy with a buffering technique referred to as split transaction memory (STM). A crucial aspect of the memory design is the memory decoding scheme. A design methodology is described for the specification of permutation matrices that yield near optimal performance for the memory system. Another important aspect of this work is the development of a software based simulator that allows a STM to be specified. The simulator, operating at the register transfer level, emulates the processing of an address stream by STM and records the events for post-processing. The STM simulator was used to evaluate three types of
Descriptors : *COMPUTER ARCHITECTURE, *PIPELINES, COMPUTER PROGRAMS, ALGORITHMS, COMPUTERIZED SIMULATION, SIMULATORS, PROCESSING EQUIPMENT, MEMORY DEVICES, VECTOR ANALYSIS, PATTERNS, FAST FOURIER TRANSFORMS, DECODING, INTERLACING.
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE