Accession Number : ADA311221
Title : Probabilistic Techniques for Reliability Analysis of VLSI Circuits.
Descriptive Note : Final rept. Aug 94-Nov 95,
Corporate Author : ILLINOIS UNIV CHAMPAIGN
Personal Author(s) : Hajj, I. N. ; Najm, F. N. ; Li, P. C. ; Goel, S. ; Saxena, V.
PDF Url : ADA311221
Report Date : JUN 1996
Pagination or Media Count : 68
Abstract : This report summarizes work done on the reliability analysis and design of VLSI circuits. Many reliability issues, such as electromigration in metal lines and hot-carrier effects (HCE) induced degradation in devices, are related to the statistics of the average current flow in the circuit and devices. New techniques for current estimation in synchronous sequential circuits have been developed and implemented. Given primary input statistics, mixed statistical Monte Carlo and probabilistic methods are applied in a mixed-mode simulation approach to estimate average currents drawn by each gate or subcircuit in the design. The results are then used for reliability estimation. In the area of design for reliability, a computer-aided design system for VLSI circuit hot-carrier reliability estimation an design was developed. The system first stimulates a circuit to determine the critical transistors that are most susceptible to hot-carrier effects based on their switching frequency and current flow through them. The system then estimates the impact of HCE on circuit delay and employs a combination of design modification and optimization strategies, including signal line reordering and gate sizing along critical paths, to eliminate or reduce HCE-induced degradation on circuit performance.
Descriptors : *VERY LARGE SCALE INTEGRATION, *RELIABILITY(ELECTRONICS), OPTIMIZATION, DEGRADATION, COMPUTER AIDED DESIGN, MODIFICATION, PROBABILITY, MONTE CARLO METHOD, SEQUENTIAL ANALYSIS, TRANSISTORS, ELECTRONIC SWITCHING, CRITICAL PATH METHODS.
Subject Categories : Electrical and Electronic Equipment
Electricity and Magnetism
Distribution Statement : APPROVED FOR PUBLIC RELEASE