Accession Number : ADA311997
Title : Neural Network Approach Towards Logic Testing and Design for Testability.
Descriptive Note : Final rept. 1 Feb 93-31 Jan 96,
Corporate Author : LOUISIANA STATE UNIV BATON ROUGE DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
Personal Author(s) : Rai, Suresh
PDF Url : ADA311997
Report Date : 01 AUG 1996
Pagination or Media Count : 13
Abstract : This report considers the problem of applying neural network for logic testing and proposes an efficient method based on the hyperneural model. The conventional Hopfield network of N neurons describes only binary relations between neurons. With this model gates having more than two inputs need hidden neurons. Even two inputs XOR and XNOR gates require four neurons; one extra than that required by most other gates. Inclusion of an additional neuron doubles the search space. Thus, finding a valid test set using Hopfield model is either increasingly hard or the network converges to an invalid solution. The proposed hyperneural model overcomes these difficulties by using an energy function that not only considers binary relations but also captures all higher order relations between N neurons. A C++ code, developed for hyperneural network (HNN) based approach, is tested on a SUN SPARC 10/41 workstation for ISCAS 85 benchmark circuits and the results are compared with those obtained from MODEM and FAN. We have also applied the hyperneural concept for redundancy identification and removal problem in combinatorial circuits. Results, obtained for benchmark circuits, compare well with those given in the literature using conventional methods.
Descriptors : *NEURAL NETS, *GATES(CIRCUITS), *SYSTEMS APPROACH, TEST AND EVALUATION, REMOVAL, MODELS, ENERGY, EFFICIENCY, CODING, STANDARDS, NERVE CELLS, MODEMS, LOGIC, REDUNDANCY, TEST SETS.
Subject Categories : Theoretical Mathematics
Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE