Accession Number : ADA321625
Title : Evaluation of the Wafer-Level Voltage Ramp Test for Oxide Integrity.
Corporate Author : ROME LAB ROME NY
Personal Author(s) : Drager, Steven L.
PDF Url : ADA321625
Report Date : DEC 1996
Pagination or Media Count : 232
Abstract : This report has two objectives. First, it provides both an overview and a critique of the Joint Electronic Devices Engineering Council (JEDEC) 14.2 Committee on Wafer Level Reliability standard, JESD-35, 'Procedure for the Wafer-Level Testing of Thin Dielectrics'. This procedure was developed to provide test data which are independent of the test equipment and the facility. This standard test methodology provides the integrated circuit user with a means of comparing the oxide quality between vendors. Second, this report provides an evaluation of the oxide quality of two DoD manufacturers. The test data shows that approximately ninety percent of the sampled oxides failed due to intrinsic breakdown, which indicates a high quality oxide. However, ten percent of the tested oxides exhibited early breakdown, which causes concern that the integrated circuits might fail during their expected lifetime.
Descriptors : *VOLTAGE, *OXIDES, *WAFERS, EXPERIMENTAL DATA, DIELECTRICS, ELECTRONIC EQUIPMENT, TEST METHODS, TEST EQUIPMENT, INTEGRATED CIRCUITS, RELIABILITY, SAMPLING, STANDARDIZATION, THINNESS, BREAKDOWN(ELECTRONIC THRESHOLD), RAMPS.
Subject Categories : Inorganic Chemistry
Electrical and Electronic Equipment
Electricity and Magnetism
Distribution Statement : APPROVED FOR PUBLIC RELEASE