Accession Number : ADA324541

Title :   Processor Management in the Tera MTA Computer System,

Corporate Author : TERA COMPUTER CO SEATTLE WA

Personal Author(s) : Alverson, Gail ; Kahan, Simon ; Korry, Richard

PDF Url : ADA324541

Report Date : 1993

Pagination or Media Count : 14

Abstract : This paper describes the processor scheduling issues specific to the Tera MTA (Multi Threaded Architecture) computer system and presents solutions to classic scheduling problems. The Tera MTA exploits parallelism at all levels, from fine-grained instruction-level parallelism within a single processor to parallel programming across processors, to multiprogramming among several applications simultaneously. Consequently, processor scheduling occurs at many levels, and managing these levels poses unique and challenging scheduling concerns. We describe the processor scheduling algorithms of the user level runtime and operating system and describe the issues relevant to each. Many of the issues encountered and solutions proposed are novel, given the multithreaded, multiprogrammed nature of our architecture.

Descriptors :   *DISTRIBUTED DATA PROCESSING, *PARALLEL PROCESSING, *SCHEDULING, *MULTIPROGRAMMING, ALGORITHMS, COMPUTER COMMUNICATIONS, COMPUTER ARCHITECTURE, CONCURRENT ENGINEERING, OPERATING SYSTEMS(COMPUTERS), MULTIPROCESSORS.

Subject Categories : Computer Systems

Distribution Statement : APPROVED FOR PUBLIC RELEASE