Accession Number : ADA326034

Title :   Soft Configurable Wafer Scale Integration: Design, Implementation and Yield Analysis.

Descriptive Note : Doctoral thesis,

Corporate Author : STANFORD UNIV CA DEPT OF COMPUTER SCIENCE

Personal Author(s) : Blatt, Miriam G.

PDF Url : ADA326034

Report Date : OCT 1990

Pagination or Media Count : 125

Abstract : Soft Configurable Wafer Scale Integration uses software controlled switches to connect up the fault-free parts of a wafer. Compared to hard configuration, the soft configurable approach has the advantages of providing low cost connections and runtime fault tolerance. The dissertation describes how to achieve soft configuration with high performance, presenting a pipelined memory system implemented using this approach. The yield of the prototype is evaluated in two phases. Fault simulation applies measured defect statistics to the layout to predict the yield of each circuit unit. These unit yields are combined to produce wafer yields using redundancy models appropriate to wafer scale integration. The redundancy models constrain wafer yield by system requirements such as the minimum number of working circuit units, and whether these working units are distributed evenly around the wafer. Choice of redundancy model significantly affects the resulting wafer yield.

Descriptors :   *COMPUTER PROGRAMS, *CIRCUIT BOARDS, *WAFERS, COMPUTERIZED SIMULATION, LOW COSTS, THESES, INTEGRATION, CONFIGURATIONS, PACKING DENSITY, REDUNDANCY, FAULT TOLERANCE, SWITCHES.

Subject Categories : Electrical and Electronic Equipment
      Computer Programming and Software
      Test Facilities, Equipment and Methods

Distribution Statement : APPROVED FOR PUBLIC RELEASE