Accession Number : ADA328450

Title :   Defects and Impurities in 4H- and 6H-SiC Homoepitaxial Layers: Identification, Origin, Effect on Properties of Ohmic Contacts and Insulating Layers and Reduction

Descriptive Note : Quarterly technical rept. 1 Apr 97-30 Jun 97,

Corporate Author : NORTH CAROLINA STATE UNIV AT RALEIGH

Personal Author(s) : Davis, R. F. ; Aboelfotoh, M. O. ; Baliga, B. J. ; Nemanich, R. J.

PDF Url : ADA328450

Report Date : JUN 1997

Pagination or Media Count : 33

Abstract : Chemical vapor deposition systems are being fabricated to deposit 4H- and 6H-SiC thin films at moderate and very high temperatures. Single crystalline A1N films with smooth surfaces were grown using gas-source MBE and characterized with RHEED, XRD, TEM and SIMS. The C-V characteristics of All A1N/SiC heterostructures depended strongly on temperature from 200 to 573 K and exhibited hysteresis effects consistent with the presence of slow interface traps. The A1N/SiC interface had a density of trapped negative charge of 3x10(exp 11)/sq cm at 27 deg C; it decreased with increasing temperature. A three-step process involving surface preparation, initial insulator formation, and oxide deposition was developed for investigation of oxide growth on 6H- and 4H-SiC. Films of SiO2 have been deposited at approx. 10 A/min for characterization. Measured impact ionization coefficient data indicate that the reverse breakdown voltage of 6H- and 4H-SiC devices should increase with temperature. This data shows that Baliga's figure of merit increases by approx. 1.5 and approx. 1.8 for 6H- and 4H-SiC, respectively, indicating superior specific on resistance for SiC field effect transistors relative to that projected earlier. Electron inversion layer mobilities of 110 sq cm/Vs (the highest reported to date) and 160 sq cm/Vs (the first reported value) have been measured in 6H- and 4H-SiC lateral MOSFETs. The devices were fabricated using a non-selfaligned process. A low temperature deposited oxide (LTO) subjected to different oxidizing and inert anneals was used as the gate dielectric.

Descriptors :   *INSULATION, *EPITAXIAL GROWTH, *IMPURITIES, *SILICON CARBIDES, *ELECTRIC CONTACTS, *DEFECT ANALYSIS, ANNEALING, LOW TEMPERATURE, INTERFACES, LAYERS, HIGH TEMPERATURE, THIN FILMS, VOLTAGE, CHEMICAL VAPOR DEPOSITION, TRAPPING(CHARGED PARTICLES), FIELD EFFECT TRANSISTORS, CRYSTALS, METAL OXIDE SEMICONDUCTORS, NITRIDES, REDUCTION, SURFACES, OXIDATION, OXIDES, ALUMINUM, REVERSIBLE, IONIZATION, HETEROGENEITY, INVERSION, INERT MATERIALS, HYSTERESIS, FIGURE OF MERIT, BREAKDOWN(ELECTRONIC THRESHOLD), SOLID STATE PHYSICS, TRANSISTORS, ELECTRON MOBILITY, MOLECULAR BEAM EPITAXY.

Subject Categories : Inorganic Chemistry
      Electrical and Electronic Equipment
      Crystallography
      Electricity and Magnetism

Distribution Statement : APPROVED FOR PUBLIC RELEASE