Accession Number : ADA329387
Title : Combinational Logic Synthesis Research Report for Advanced Logic Synthesis for Low Power Mobile Applications Project
Corporate Author : CADENCE DESIGN SYSTEMS INC BERKELEY CA
Personal Author(s) : Saldanha, Alexander ; Simion, Viorica
PDF Url : ADA329387
Report Date : AUG 1997
Pagination or Media Count : 18
Abstract : Timed Shannon Circuits have been proposed as a low-power circuit design style 1 with the attractive properties of providing predictable, delay-insensitive low-power dissipation. In this report we present the results of a comprehensive evaluation to compare the designs generated using Timed Shannon Circuits versus those generated by a commercial logic synthesis program (Synergy).
Descriptors : *LOGIC CIRCUITS, LOW POWER, OPTIMIZATION, DESIGN CRITERIA, TIMING CIRCUITS.
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE