Accession Number : ADA335548
Title : Ground Terminal Processor Interface Board for Skynet Uplink Synchronization Trials
Corporate Author : DEFENCE RESEARCH ESTABLISHMENT OTTAWA (ONTARIO)
Personal Author(s) : Tom, Caroline
PDF Url : ADA335548
Report Date : NOV 1997
Pagination or Media Count : 56
Abstract : A ground terminal (GT) simulator subsystem is being developed at Defence Research Establishment Ottawa (DREO) as part of the in-house work examining the aspects of uplink synchronization for extremely-high-frequency (EHF) spread spectrum satellite communications (SATCOM). Requirements of the GT subsystem include the generation of hop clock and data clock signals, and the interface between the GT processor and a hopping synthesizer controller (HSC) for commanding the HSC and transmitting data. A GT processor interface (i/f) board was designed and fabricated at DREO to satisfy these requirements. This report describes the functions of the i/f board and specific requirements related to the uplink synchronization experiments and the interface to the HSC. The i/f board is a printed circuit board which is contained in a backplane chassis and is driven by the GT processor. The GT processor is realized by a Spectrum Signal Processing Inc. TMS320C30 digital signal processor board and communicates with the GT processor i/f board via the DSPLINK interface through the backplane. This report includes implementation details of the clock generation and interface circuitry and a user's guide for the proper configuration, installation and operation of the GT processor i/f board.
Descriptors : *SATELLITE COMMUNICATIONS, *SYNCHRONIZATION(ELECTRONICS), *UPLINKS, *COMMUNICATION SATELLITE TERMINALS, SIGNAL PROCESSING, CLOCKS, CANADA, DATA LINKS, EXTREMELY HIGH FREQUENCY, PRINTED CIRCUIT BOARDS, SPREAD SPECTRUM.
Subject Categories : Non-radio Communications
Distribution Statement : APPROVED FOR PUBLIC RELEASE