Accession Number : ADD000065
Title : Method of Making Epoxy Tunnel Structure for Plated Wire Memories.
Descriptive Note : Patent,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C
Personal Author(s) : Bonfiglio,Guy P ; Farris,Joseph P
Report Date : 30 Oct 1973
Pagination or Media Count : 11
Abstract : The patent describes a process for fabricating a memory plane for a plated wire memory stack. A plurality of tunnel-forming wires coated with lubricant are straightened under tension and deployed over a bottom sheet of epoxy material. The sheet is covered with epoxy resin up to the wires and strips of epoxy material are then placed over the bottom sheet to either side of the wires to define wire array cavities. Additional epoxy resin is then applied filling the cavities and covering the strips after which a top sheet of epoxy is laid down. After the assembly is cured, the tunnel-forming wires are withdrawn and plated wires are inserted into the resultant holes in the word pack.
Descriptors : *Memory devices, *Patents, Fabrication, Laminates, Wire, Epoxy resins
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE