Accession Number : ADD000073

Title :   Current Limiting Integrated Circuit.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C

Personal Author(s) : White,Joseph P ; Amantea,Robert ; Becke,Hans W

Report Date : 30 Oct 1973

Pagination or Media Count : 5

Abstract : The patent describes an integrated circuit having a laminated bipolar transistor with multi-emitters respectively serially connected to a plurality of deep depletion field effect transistors and/or inversion channel field effect transistors. The integrated circuit has a common layer functioning as both the drain of one of the field effect transistors and an emitter of the bipolar transistor. In operation the field effect transistors conduct currents in series with the respective emitters of the bipolar transistor. In addition the field effect transistors provide ballasting by limiting the current therethrough.

Descriptors :   *Current limiters, *Integrated circuits, *Patents, Transistors

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE