Accession Number : ADD000296

Title :   Processor Synchronization Scheme.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C

Personal Author(s) : Zieve,Robert M ; Maginnis,Christopher L ; Kleidermacher,Moishe

Report Date : 04 May 1971

Pagination or Media Count : 6

Abstract : The patent describes a method of maintaining synchronization between two independently clocked, stored-program computer processors which are executing the same program simultaneously and are connected in a master-slave relationship. There is further provided a method of preventing a failure from disabling both master and slave units. A special function is inserted at selected intervals which delays the master processor until the slave processor catches up. Further, means are provided to automatically detect when a failure occurs. This program alignment and error detection are accomplished by inserting checkpoints at selected intervals at which the redundantly processed results are compared.

Descriptors :   *Data processing, *Synchronization(Electronics), *Patents, Redundant components, Computer programming, Parallel processing

Subject Categories : Computer Programming and Software

Distribution Statement : APPROVED FOR PUBLIC RELEASE