Accession Number : ADD000582

Title :   Clock Synchronization System.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON D C

Personal Author(s) : Willmore,Robert R

Report Date : 25 Mar 1975

Pagination or Media Count : 9

Abstract : The patent describes a synchronizing apparatus having a phase sensitive zero crossing detector fed to a voltage controlled integrator and a box car circuit that is also fed by the voltage controlled integrator. The output of a sweep controlled difference integrator fed by the box car circuit is summed with the box car circuit output and fed the voltage controlled integrator and a voltage controlled multivibrator, the output thereof being fed to the zero crossing detector.

Descriptors :   *Synchronism, *Patents, Clocks, Circuits, Phase, Sensitivity, Synchronization(Electronics)

Subject Categories : Test Facilities, Equipment and Methods

Distribution Statement : APPROVED FOR PUBLIC RELEASE