Accession Number : ADD001344

Title :   High Speed Random Access Memory Shift Register.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C

Personal Author(s) : Leibowitz,Lawrence M ; Bates,Charles F

Report Date : 16 Jul 1974

Pagination or Media Count : 6

Abstract : The patent relates to a number of random-access memory (RAM) units controlled by read-write logic, memory address counters, and a clock distribution function to provide a high speed shift register. The high speed capability is obtained through the use of a plurality of lower speed RAMs by sequentially processing input data from the first RAM to the second, then the third, etc. The output is taken from each RAM and fed to a latch so that while one RAM is providing data as an output, a subsequent RAM is able to manipulate and operate on subsequent data. Extremely long, high speed shift registers may be realized by this invention with particular interest in the area of signal processing of radar video returns.

Descriptors :   *Shift registers, *Patents, Random access computer storage, Signal processing, Computer logic

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE