Accession Number : ADD002914
Title : High-Speed Adder.
Descriptive Note : Patent,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C
Personal Author(s) : Gehweiler,William Frederick ; Pridgen,Junius Issac
Report Date : 20 Jul 1976
Pagination or Media Count : 13
Abstract : The patent describes a high-speed adder circuit capable of performing addition with binary numbers in 1's complement, 2's complement or sign-magnitude formats. The adder can be made in the form of a single chip that can be assembled in multiple units to expand its capacity. There is a provision for converting minus zero to plus zero so as to prevent oscillations from occurring in the loop circuit. Also, the sum output is automatically shifted to the correct format when an overflow condition occurs.
Descriptors : *Arithmetic units, *Patents, Logic circuits, Digital computers
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE