Accession Number : ADD003542
Title : Digital Bypassable Register Interface.
Descriptive Note : Patent Application,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C
Personal Author(s) : Wilcox,Dwight R
Report Date : 22 Feb 1977
Pagination or Media Count : 14
Abstract : An interface for transmitting data in either a clock edge triggered synchronous transmission mode or an asynchronous transmission mode is described. An edge triggered register has its input connected to a source of digital data and its output connected to a two-to-one multiplexer. A bypass path connected between the digital data source and the multiplexer is provided around the edge triggered register. The two-to-one multiplexer is selectively actuable to provide either asynchronous transmission by connecting the bypass path to an output means or to provide synchronous transmission by connecting the output of the edge triggered register to the output means.
Descriptors : *Patent applications, *Registers(Circuits), Interfaces, *Buffer storage, Trigger circuits, Synchronization(Electronics), Modules(Electronics), Clocks, Data transmission systems, Transistor transistor logic, Digital systems, Multiplexing, Amplifiers
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE