Accession Number : ADD004069

Title :   High Speed Serial Data Synchronization Scheme.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON D C

Personal Author(s) : Symanski,Jerome J

Report Date : 29 Mar 1977

Pagination or Media Count : 4

Abstract : A serial-to-parallel data conversion and synchronization scheme in which a plurality of active logic elements are utilized as delay lines. Each of the delay lines introduces a delay equal to the period of one data bit and one additional delay line introduces a delay equal to one half the period of a data bit. The input of the first delay line is connected to the data input of a first flip-flop and the outputs of each of the plurality of delay lines are each connected to the data input of a flip-flop. The output of the additional delay line is connected to the clock inputs of each of the flip-flops whereby the serial data word is converted to a parallel data word and the conversion is internally clocked by the delay lines themselves. (Author)

Descriptors :   *Patents, *Data processing equipment, *Synchronization(Electronics), Serial processors, High velocity, Delay lines, Logic elements

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE