Accession Number : ADD004193

Title :   Pulse Peak Sample and Hold Circuit.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON D C

Personal Author(s) : May,Klaus D ; Nasuta,Anthony T , Jr

Report Date : 26 Jul 1977

Pagination or Media Count : 5

Abstract : A pulse peak sample and hold circuit includes a passive input integrator to develop the time of a sample gate. A sensitive comparator develops the gate pulse. A FET and storage capacitor 'holds' the actual input amplitude. The circuit is independent of PRF and pulse width. (Author)

Descriptors :   *Patents, *Pulse amplitude, *Samplers, *Peak values, *Storage, *Circuits, Gates(Circuits), Comparators, Field effect transistors, Capacitors

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE