Accession Number : ADD004421

Title :   Drain Source Protected MNOS Transistor and Method of Manufacture.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON D C

Personal Author(s) : Blaha,Franklyn C ; Cricchi,James R ; White,Marvin H

Report Date : 11 Oct 1977

Pagination or Media Count : 5

Abstract : An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions. (Author)

Descriptors :   *Patents, *Field effect transistors, *Radiation hardening, *Metal nitride oxide semiconductors, Masking, Fabrication, Silicon Dioxide, Layers

Subject Categories : Electrical and Electronic Equipment
      Mfg & Industrial Eng & Control of Product Sys
      Nuclear Radiation Shield, Protection & Safety
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE