Accession Number : ADD005272

Title :   MNOS Memory Transistor having a Redeposited Silicon Nitride Gate Dielectric.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON D C

Personal Author(s) : Blaha,Franklyn C ; Cricchi,James R

Report Date : 20 Jun 1978

Pagination or Media Count : 8

Abstract : A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes. (Author)

Descriptors :   *Patents, *Metal nitride oxide semiconductors, *Silicon nitrides, *Transistors, *Memory devices, Gates(Circuits), Oxides, Interfaces

Subject Categories : Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE