Accession Number : ADD005501

Title :   Verification Technique for Checking Wrapped Wire Electronic Boards.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE ARMY WASHINGTON D C

Personal Author(s) : Marcus,Ira R ; Lee,Albert

Report Date : 23 May 1978

Pagination or Media Count : 7

Abstract : Describes a verification technique which greatly simplifies and facilitates the testing of the wiring of wrapped wire electronic boards. The technique contemplates continuity testing of each branch and discontinuity testing between successive branches. After a continuity test for one branch and a discontinuity test with the next succeeding branch, the two branches are then short-circuited. The procedure is repeated with each wired branch until all branches have been tested, whereupon the short-circuit wire may then be removed. The testing technique may be facilitated by utilizing a numerically controlled terminal locator in combination with a computer generated control tape. The technique also contemplates a visual check to verify that all pins on the board that are intended to be wired are indeed wired, and that all pins on the board which are not intended to be wired are indeed bare. (Author)

Descriptors :   *Patents, *Circuit boards, *Circuit testers, *Electric wire, Continuity, Substrates, Pins, Short circuits

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE