Accession Number : ADD005997

Title :   Failureresistant Pseudo-Nonvolatile Memory.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Gariazzo,Michael C ; Haynes,Leonard S

Report Date : 02 Jan 1979

Pagination or Media Count : 5

Abstract : Disclosed is a plurality of parallel resistive-capactive clamping circuits individually coupling the bit 'input' and bit 'output' terminals of a multi-bit, serial/parallel (S/P), synchronous/asynchronous (S/A) shift register (e.g., CD-4034A). The clamping circuits provide the contents of the shift register with an increased immunity from the effects of transients, radiation, and temporary power failures. (Author)

Descriptors :   *Patents, *Nonvolatile memories, *Shift registers, Integrated circuits, Reliability(Electronics), Data storage systems, Transients, Failure(Electronics), Resistance

Subject Categories : Electrical and Electronic Equipment
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE