
Accession Number : ADD006434
Title : Permutation Memories.
Descriptive Note : Patent,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Whitehouse ,Harper J ; Speiser,Jeffrey M
Report Date : 07 Aug 1979
Pagination or Media Count : 9
Abstract : A permutation memory comprises an input control means for decoding, having a plurality L of inputs for an Lbit binary number, and a plurality 2 superscript L of outputs. Means are connected to the decoding means, for initiating the readin of the Lbit number. Means are provided for applying an input signal. A first plurality of 2 superscript L of normally open switching means are connected to the 2 superscript L outputs of the decoding means and to the signal applying means. A plurality of 2 superscript L of means are connected to the switching means, for storing a charge when a specific switching means, connected to a corresponding charge storing means, is in a closed condition. A second plurality 2 superscript L of switching means are connected to the first plurality of switching means and to the charge storing means. An output control means, connected to the second plurality of switching means, reads out the states of the 2 superscript L chargestoring means, as to the amount of charge in each. Means are connected to the readout means, for initiating the readout. (Author)
Descriptors : *Patents, *Signal processing, *Memory devices, *Permutations, Transformations(Mathematics), Discrete Fourier transform, Input output processing, Binary notation, Decoding, Switching circuits
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE