Accession Number : ADD007580

Title :   False Count Correction in Feedback Shift Registers and Pulse Generators Using Feedback Shift Registers.

Descriptive Note : Patent Application,

Corporate Author : DEPARTMENT OF THE ARMY WASHINGTON DC

Personal Author(s) : Rittenbach,Otto E

Report Date : 17 Jun 1980

Pagination or Media Count : 17

Abstract : A pulse train generator is described which includes a shift register with feedback for producing an output pulse for every m clock pulses applied to the shift register stages. The feedback shift register normally has a maximal length -2 to the n power -1, where n is the number of stages. Clock pulses are applied to the shift register until an all-ONE condition is reached; thereupon, (m-1) additional clock pulses, where m can be less than n, are applied and the states of the register stages can then be sensed. Appropriate gate circuits are added to the shift register, including an n-input inverting AND gate, depending upon the sensed register states, to inhibit certain shifts and to insure that the register is returned to the all-ONE condition upon arrival of every mth clock pulse. The pulse generator referred to above provides means for obtaining an output pulse for every m bits of the code length.

Descriptors :   *Patent applications, *Pulse generators, *Shift registers, Nand gates, Inverter circuits, Clocks, Feedback, Length, Output, Coding

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE