Accession Number : ADD008069

Title :   Self-Aligned Recessed Gate with Low Source Resistance.

Descriptive Note : Patent Application,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Bandy,Steve Gray ; Nishimoto,Clifford

Report Date : 16 Jun 1980

Pagination or Media Count : 9

Abstract : A self-aligned recessed gate with low source resistance has an epitaxial structure with an n(+) contact layer. Source and drain contacts are put down, followed by resist spin-on and gate exposure. The gate channel is anodically thinned to expose the n active layer. The gate metal is evaporatively applied through the same resist opening which defines the gate channel. An insulating layer is laid down between the resist and the FET structure with ohmic contacts to prevent resist lifting, and a barrier layer is put over the ohmic contacts to provide insulating layer adhesion. The result is a sub-micron gate length FET having low source impedance. (Author)

Descriptors :   *Patent applications, *Gates(Circuits), *Field effect transistors, Exposure(General), Epitaxial growth, Electric contacts, Insulation, Structures, Adhesion, Channels, Layers, Length, Barriers, Spinners

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE