Accession Number : ADD008423

Title :   Silicon Barrier Josephson Junction Configuration.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Davis,Kenneth L

Report Date : 03 Mar 1981

Pagination or Media Count : 6

Abstract : This abstract describes a planar, silicon barrier, Josephson junction and method of forming the junction which does not require expensive high-resolution, lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties.

Descriptors :   *Patents, *Josephson junctions, *Silicon, *Wafers, *Etching, Processing, Masks, Superconductors, Films, Single crystals, Barriers, Inventions

Subject Categories : Mfg & Industrial Eng & Control of Product Sys
      Quantum Theory and Relativity

Distribution Statement : APPROVED FOR PUBLIC RELEASE