Accession Number : ADD008983

Title :   Planar Doped Barrier Transistor.

Descriptive Note : Patent Application,


Personal Author(s) : Malik,Roger J ; Eastman,Lester F ; Hollis,Mark A

Report Date : 08 Sep 1981

Pagination or Media Count : 12

Abstract : Disclosed is a three terminal epilayer semiconductor structure forming a transistor comprised of two rectifying planar doped barriers separated by an intermediate semiconductor region with the two barriers having respective predetermined barrier height characteristics which are altered upon the application of a bias potential there across and with the intermediate region providing a region for the controlled injection and collection of electrons from one of the barriers whereby majority carriers, i.e. electrons, will surmount and be swept across the other barrier when the peak of the other barrier is below the peak of the first barrier as a result of the applied bias. The device is fabricated by an epitaxial growth process which results in an n+ - i - p+ - i - n structure forming the first or outer barrier, while the other or underlying barrier comprises an n - i - p+ - i - n+ structure with the intermediate region consisting of a portion of the n layer common to both barriers. The composite structure, moreover, utilizes interdigited ohmic contacts for two of the terminals defining the emitter and base contacts of the transistor to minimize the series resistances and capacitances associated with the device. (Author)

Descriptors :   *Patent applications, *Planar structures, *Transistors, *Doping, *Barriers, *Semiconductor diodes, Extremely high frequency, Composite structures, P type semiconductors, Electric contacts, N type semiconductors, Growth(General), Terminals, Structures, Layers, Capacitance, Injection, Regions, Height, Electrons, Control, External, Collection, Bias

Subject Categories : Electrical and Electronic Equipment
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE