Accession Number : ADD008984
Title : Automated Universal Array.
Descriptive Note : Patent Application,
Corporate Author : DEPARTMENT OF THE ARMY WASHINGTON DC
Personal Author(s) : Borgini,Fred ; Noto,Richard
Report Date : 28 Sep 1981
Pagination or Media Count : 20
Abstract : This abstract disclose a large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing. Interconnection and vertical signal routing between cell rows can be made through a feedthrough in each internal cell and connection to selective vertical tunnels without touching the overhead horizontal wiring channels which provide horizontal signal routing.
Descriptors : *Patent applications, *Integrated circuits, *Routing, *Arrays, *Automation, *Logic circuits, Passive systems, NAND gates, Complementary metal oxide semiconductors, Vertical orientation, Horizontal orientation, Foundations(Structures), Signal processing, Transistors, Diodes, Functions, Tunnels, Parts, Internal, Patterns, Circuits, Cells, Global, Logic
Subject Categories : Electrical and Electronic Equipment
Solid State Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE