Accession Number : ADD009441

Title :   Simplified Fabrication Method for High-Performance Fet.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Yoder,Max N

Report Date : 17 Dec 1980

Pagination or Media Count : 5

Abstract : A method for making reproducible FET's with gate dimensions in the submicrometer range, reduced source-gate channel resistance, and reduced gate and source contact resistances comprising forming, in order, on a semi-insulating substrate, of GaAs, an N-type GaAs layer, an (N+) GaAs layer and an (N(+)+) Ge layer, using a photolith process with a mask to form the gate channel region therein, forming a refractory metal layer covering the whole top of the device, forming a gold layer on the refractory metal, using a photolith method with a common mask and etch process to cut the gate, source and drain electrodes to their desired sizes and using a plasma etch process to cut away, except for a stalk supporting the gate Au electrode, the remaining refractory metal from a portion of the gate channel lying between the gate and source electrode region and lying between the gate and drain electrode region. (Author)

Descriptors :   *Patents, *Field effect transistors, *Fabrication, *Methodology, High rate, Performance(Engineering), Electrodes, Drainage, Gates(Circuits), Etching, Layers, Gold, Inventions, Refractory metals, Insulation, Resistance, Electrodes

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE