Accession Number : ADD009758

Title :   Process for Preparing Isolated Junctions in Thin-Film Semiconductors Utilizing Shadow Masked Deposition to Form Graded-Side Mesas.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Morris,Hayden ; Bis,Richard F

Report Date : 25 May 1982

Pagination or Media Count : 10

Abstract : A controlled environment process for making diode arrays by depositing the sublimate of a semiconductor material through an aperture of a mask placed nearby a substrate and then subjecting part of the sublimate to ion implantation. The aperture causes diffraction of the sublimate vapor stream while the proximity of the edges of the aperture to the substrate causes the central plateau of the deposited thin-film to have a rounded rim leading to sides that taper smoothly in thickness to the substrate. Ion implantation to a controlled depth creates an isolated planar junction. Surface layers of a gold electrode running onto the substrate from different surface areas of the thin-film provide for off-mesa bonding of electrical leads.

Descriptors :   *Patents, *Processing, *Diodes, *Arrays, *Deposition, Electric connectors, Semiconductors, Thin films, Substrates, Ion implantation, Vapor deposition, Electrodes, Gold, Inventions, Electrochemistry, Junctions, Planar structures

Subject Categories : Fabrication Metallurgy

Distribution Statement : APPROVED FOR PUBLIC RELEASE