Accession Number : ADD010153

Title :   Silicon Barrier Josephson Junction Configuration.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Davis,Kenneth L

Report Date : 11 Jan 1983

Pagination or Media Count : 5

Abstract : A planar, silicon barrier, Josephson junction and method of forming the junction which does not require expensive high-resolution lithography techniques such as electron beam or x-ray. The method includes an etching mask-etch process which forms the basic structure configuration using a (110)-cut silicon wafer. Subsequent to the etching process the mask is removed and a superconducting film is deposited on the previously formed silicon surface to produce a single crystal silicon barrier with good electrical properties. (Author)

Descriptors :   *Patents, *Josephson junctions, *Barriers, *Silicon, *Superconductors, Wafers, Single crystals, Surfaces, Electrical properties, Configurations, High resolution, Lithography, Electron beams, Cutting, Etching, Structures

Subject Categories : Electrical and Electronic Equipment
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE