Accession Number : ADD011128

Title :   Programmable Arithmetic Logic Unit.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON DC

Personal Author(s) : Miller,G I

Report Date : 12 Jun 1984

Pagination or Media Count : 4

Abstract : A programmable arithmetic logic unit for performing high speed bit sliced, pipelined computations at very low power is fabricated as a LSI component using CMOS/SOS technology. It is microprogrammable and operates in conjunction with a fast microprogram store program memory and controller. Dual input ports which supply data from eight sources are latched and operated on while new data is simultaneously fetched. Instruction bits shift data in either port left or right, select complements and select an operand between device input and output data in one port. The data processed in each port is compared and is added to provide a latched tri-state output to an external device. (Author)

Descriptors :   *Patents, *Arithmetic units, *Computer logic, High velocity, Microprogramming, Low power, Input output processing, Complementary metal oxide semiconductors, Signal processing, Memory devices

Subject Categories : Computer Programming and Software
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE