Accession Number : ADD011500

Title :   Method for the Fabrication of Dielectric Isolated Junction Field Effect Transistor and PNP Transistor.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON DC

Personal Author(s) : Cunniff,K F

Report Date : 13 Nov 1984

Pagination or Media Count : 6

Abstract : The process of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor on a common substrate. An epitaxially layer is deposited on the base substrate to form the channel region of the junction field effect transistor. Impurities for the source and drain of the field effect transistor are diffused into the epitaxial layer. Impurities to form the gate are diffused into the epitaxially layer between the source and gate regions but separated therefrom. The PNP transistor which is dielectrically isolated from the field effect transistor by grooves, is formed by the diffusion into the base substrate of the respective impurities that form the base, collector and emitter regions of the PNP transistor. (Author).

Descriptors :   *Patents, *Semiconductor devices, *Dielectric properties, *Integrated circuits, *Fabrication, Junction transistors, Field effect transistors, PNP transistors, Impurities, Silicon compounds, Polysilicons, Isolation, Etching, Polycrystalline, Epitaxial growth

Subject Categories : Electrical and Electronic Equipment
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE