Accession Number : ADD011536
Title : Process for Making a Heterojunction Source-Drain Insulated Gate Field-Effect Transistors Utilizing Diffusion to Form the Lattice.
Descriptive Note : Patent,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Wieder,H H ; Clawson,A R
Report Date : 04 Sep 1984
Pagination or Media Count : 4
Abstract : An apparatus for and a method of making heterojunction source-drain insulated gate field-effect transistors in order to obtain higher gain-bandwidth products at microwave frequencies. A semi-insulating InP semiconductor substrate is provided with a ternary alloy layer of p-type Ga0.47In0.53As, or optionally, an acceptor-doped p-type bulk of Ga0.47In0.53As can be substituted. Troughs are shaped in the substrate and layer for receiving a material lattice-matched to the n+ p-type Ga0.47In0.53As to perform as the source and drain contacts, n+ doped InP might be a suitable material. An optional method for forming the contacts calls for directing a stream of phosphine and hydrogen onto source and drain contact windows contacting the Ga0.47In0.53As which is heated to 750 deg C. for about 15 minutes. This creates graded heterojunction source and drain contacts having a lattice-matching variable composition.
Descriptors : *Patents, *Heterojunctions, *Field effect transistors, *Semiconductors, Substrates, Bandwidth, Gain, Microwave frequency, Phosphine, Ternary compounds, N type semiconductors, P type semiconductors, Indium compounds, Gallium compounds, Gates(Circuits)
Subject Categories : Solid State Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE