Accession Number : ADD011909
Title : Three-Stage Binary Coincidence Detector Apparatus with Adaptive Constant False Alarm Rate.
Descriptive Note : Patent,
Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON DC
Personal Author(s) : Justus,J J
Report Date : 11 Jun 1985
Pagination or Media Count : 4
Abstract : A target processor utilizing a feedback loop to maintain a constant false alarm rate for variable level video input signals with noise or noise plus clutter on the imput signal. The processor includes three serially connected stages of binary coincidence detectors which comprise a threshold detector for processign video signals which exceed a threshold level, an M of N detector for providing an alarm for each range having a count of M or greater pulses. and a P of Q detector for generating a target alarm after at least P or greater frequencies have been transmitted.
Descriptors : *PATENTS, *SIGNAL PROCESSING, *DETECTORS, *VIDEO SIGNALS, TARGET DETECTION, FREQUENCY, ADAPTIVE SYSTEMS, COINCIDENCE COUNTING, COUNTING METHODS, PROCESSING EQUIPMENT, TARGETS, THRESHOLD EFFECTS, FALSE ALARMS, RATES, FEEDBACK, LOOPS, WARNING SYSTEMS
Subject Categories : Non-radio Communications
Distribution Statement : APPROVED FOR PUBLIC RELEASE