Accession Number : ADD011914

Title :   Quasi-Accumulation Mode FET.

Descriptive Note : Patent Application,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Yoder,M N

Report Date : 20 Aug 1985

Pagination or Media Count : 25

Abstract : A Field Effect Transistor (FET) capable with standing increased positive gate biasing with respect to the source contact without incurring the penalty of drawing excessive gate current, comprising a semi-insulating substrate layer; and active channel layer of doped n-type semi-conductor material disposed on the substrate layer; an active channel layer of doped n-type semi-conductor material disposed on the substrate layer; a first heteroepitaxial semi-insulating layer of a semi-insulating material having a bandgap greater than the bandgap of the active channel layer material disposed on said active channel layer. The first heteroepitaxial layer has a top surface, a designated first region, designated second region, adn a designated middle section disposed therebetween wherein the first region and the second region, and a designated middle section dispose there between wherein the first region and the second region of the first heteroepitaxial layer are implanted with activated donor impurities to form its source and drain regions. The device is also provided with conventional source, drain and gate contacts. In a preferred embodiment, a heavily donor doped Gallium arsenide heteroepitaxial layer is disposed between the source contact and the first heteroepitaxial layer and between the drain contact and the first heteroepitaxial layer.

Descriptors :   *PATENT APPLICATIONS, *EPITAXIAL GROWTH, *FIELD EFFECT TRANSISTORS, *SUBSTRATES, ACTIVATION, IMPURITIES, CHANNELS, LAYERS, SOURCES, ENGINEERING DRAWINGS, INSULATION, MATERIALS, BIAS, GATES(CIRCUITS), PENALTIES

Subject Categories : Electrical and Electronic Equipment
      Crystallography

Distribution Statement : APPROVED FOR PUBLIC RELEASE