Accession Number : ADD011955

Title :   Relative Sizing of Layout Data to Compensate for Exposure Errors on Optical Lithography Systems.

Descriptive Note : Patent Application,

Corporate Author : DEPARTMENT OF THE ARMY WASHINGTON DC

Personal Author(s) : Chatterjee,Pallab K

Report Date : 28 Nov 1985

Pagination or Media Count : 7

Abstract : The processing of advance integrated circuits oftentimes employs the patterning of fine geometries of differing levels. This leads to a non-uniform thickness of photo-resist about the topologies and a built-in defocus for the optical projection lithography used to fabricate the integrated circuit itself. In the processing of these advanced integrated circuits according to the invention, the data is to be laid out with a predetermined reticule sizing based on the topological characteristics then of concern, so as to compensate for the defocussing previously associated with a single layer photo-resist process. (Author)

Descriptors :   PATENT APPLICATIONS, *PHOTOLITHOGRAPHY, *INTEGRATED CIRCUITS, THICKNESS, RETICULAR FORMATION

Subject Categories : Electrical and Electronic Equipment
      Mfg & Industrial Eng & Control of Product Sys
      Printing and Graphic Arts

Distribution Statement : APPROVED FOR PUBLIC RELEASE