Accession Number : ADD012208

Title :   Apparatus and Method for Aligning a Mask and Wafer in the Fabrication of Integrated Circuits.

Descriptive Note : Patent,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Bass,John F ; Saks,Nelson ; Peckerar,Martin

Report Date : 04 Feb 1986

Pagination or Media Count : 8

Abstract : An apparatus and method for aligning a mask and wafer in the fabrication of integrated circuits utilizing alignment patterns on the mask and wafer. Each alignment pattern comprises a plurality of parallel alignment marks which are spaced from one another such that the patterns may be superimposed so that the marks of one pattern are positioned between marks of the other pattern. When the patterns are misaligned, a moire pattern is produced which disappears on alignment. The marks of each pattern are also disparaately spaced from one another, permitting a gross to fine alignment. In aligning the patterns, each mark of one pattern is positioned between pairs fo marks of the other pattern in an order corresponding to the widths of spaces defined between marks of the other pattern, progressing from the largest space width, giving gross alighment, to the smallest, giving fine alignment. (Author)

Descriptors :   *PATENTS, *SEMICONDUCTOR DEVICES, *INTEGRATED CIRCUITS, *ALIGNMENT, *MASKS, FABRICATION, PATTERNS, WAFERS, PARALLEL ORIENTATION, SUBSTRATES, WIDTH

Subject Categories : Electrical and Electronic Equipment
      Mfg & Industrial Eng & Control of Product Sys
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE