Accession Number : ADD013576

Title :   Method of Characterizing Critical Timing Paths and Analyzing Timing Related Failure Modes in Very Large Scale Integrated Circuits.

Descriptive Note : Patent, Filed 28 Mar 85, patented 6 Oct 87,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON DC

Personal Author(s) : Burns, Daniel J ; Eldering, Charles A ; Pronobis, Mark T

Report Date : 06 Oct 1987

Pagination or Media Count : 46

Abstract : A method for characterizing critical timing paths and analyzing timing related failure modes in high clock rate photocurrent at the drain of a single transistor in a very large scale integrated circuit. The laser testing apparatus utilized with the method of this invention incorporates therein a laser having its output beam focused onto the drain junction of the transistor under test. The localized injection of electromagnetic radiation produces a photocurrent at the drain junction of the transistor at specific times during the testing procedure which increases in the minimum operating power supply and/or a decrease in the maximum operating frequency at which the microcircuit wil properly function. Consideration of these parameters and the level of photocurrent provide a measurement related to the worst case timing margin which occurs during the functional test of the integrated microcircuit.

Descriptors :   *CRITICAL PATH METHODS, *INTEGRATED SYSTEMS, *MICROCIRCUITS, *PHOTOELECTRICITY, *TRANSISTORS, *PATENTS, CLOCKS, DRAINAGE, ELECTRIC CURRENT, FAILURE, INJECTION, JUNCTIONS, LASERS, OUTPUT, RATES, TEST EQUIPMENT, TIME

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE