Accession Number : ADD014275

Title :   Easily Testable High Speed Architecture for Large Rams.

Descriptive Note : Patent, Filed 12 Jun 87, patented 23 May 89,

Corporate Author : DEPARTMENT OF THE AIR FORCE WASHINGTON DC

Personal Author(s) : Jarwala, Najmi T ; Pradhan, Dhiraj K

Report Date : 23 May 1989

Pagination or Media Count : 9

Abstract : The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The address, data and control signals are applied to the root node. The most significant address bit is decoded, generating either a left subtree or a right subtree select. The other signals would be buffered and propagated down the tree. The solution process occurs at each level within the bus until finally a single leaf node would be selected. Within the node, then, the internal timing and control unit would access the data requested, sending it up the tree or writing the value on the data bus, into the addressed location. Patents. (RRH)

Descriptors :   *ARCHITECTURE, *CONTROL SYSTEMS, *DATA MANAGEMENT, *NODES, *PATENTS, *SIGNALS, *TIMING DEVICES, CONTROL, INTERNAL, SOLUTIONS(GENERAL), TEST METHODS

Subject Categories : Electrical and Electronic Equipment
      Command, Control and Communications Systems

Distribution Statement : APPROVED FOR PUBLIC RELEASE