Accession Number : ADD015975
Title : Method for Fabricating Self-Aligned Gate Diffused Junction Field Effect Transistor.
Descriptive Note : Patent, Filed 28 Aug 92, patented 28 Sep 93,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Nguyen, Richard ; Hewett, Charles A
Report Date : 28 Sep 1993
Pagination or Media Count : 7
Abstract : A method for fabricating a self-aligned, gate diffused junction field effect transistor is provided which includes the steps of forming an n-type layer on an indium phosphide, semi-insulating substrate; forming spaced apart source/drain metal contacts on the n-type layer; forming a metal gate on the n-type layer between the spaced apart source/drain contacts, where the metal gate is insulated from the source/drain contacts and includes a metallic p-type dopant material; and forming a p-type region in the n-type layer beneath the metal gate so that the gate contact and the p-type region have coincident boundaries with respect to each other at the surface of the n-type layer. The method may also be employed to manufacture a bipolar transistor by allowing the self-aligned and diffused p-type region to extend through the n-type layer to the semi-insulating substrate.
Descriptors : *FIELD EFFECT TRANSISTORS, *PATENTS, *GATES(CIRCUITS), *JUNCTION TRANSISTORS, BIPOLAR TRANSISTORS, BOUNDARIES, INDIUM PHOSPHIDES, LAYERS, MATERIALS, METAL CONTACTS, SUBSTRATES, SURFACES, FABRICATION, DIFFUSION
Subject Categories : Electrical and Electronic Equipment
Electricity and Magnetism
Distribution Statement : APPROVED FOR PUBLIC RELEASE