Accession Number : ADD016255
Title : Uninterrupted, Enhanced-Rate Event Sequencer With Mixed-Speed Counter Modules.
Descriptive Note : Patent, Filed 18 Dec 91, patented 5 Apr 94,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Cronyn, Willard M
Report Date : 05 Apr 1994
Pagination or Media Count : 9
Abstract : The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a 'steady state' count at a scheduled event time.
Descriptors : *COUNTERS, *PATENTS, *MODULES(ELECTRONICS), CLOCKS, INVENTIONS, SWITCHES, TIME
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE