Accession Number : ADD017307

Title :   Fabrication Method for III-V Heterostructure Field-Effect Transistors.

Descriptive Note : Patent, Filed 29 Jan 93, patented 15 Nov 94,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Boos, J B ; Kruppa, Walter

Report Date : 15 Nov 1994

Pagination or Media Count : 16

Abstract : A heterojunction device, and a method for producing the device. A gate air bridge is formed at the mesa sidewall between the active region and the gate bonding pad to lower the gate leakage current. The device has a double recessed gate to reduce local fields in the vicinity of the gate. The fabrication method uses dielectric intermediate and final passivation layers to optimize the double-recess profile and control the extension of the high-field region between the gate and the drain. This combination increases the breakdown potential of the device, but minimizes the effective gate length of the device, preserving high frequency performance. (jg)

Descriptors :   *HETEROJUNCTIONS, *GATES(CIRCUITS), *FIELD EFFECT TRANSISTORS, *GROUP IV COMPOUNDS, *PATENTS, HIGH FREQUENCY, AIR, LAYERS, DIELECTRICS, FABRICATION, REGIONS, LENGTH, HETEROGENEITY, GROUP III COMPOUNDS, GROUP V COMPOUNDS, LEAKAGE(ELECTRICAL), BRIDGES, PASSIVITY

Subject Categories : Electrical and Electronic Equipment
      Inorganic Chemistry
      Physical Chemistry
      Electricity and Magnetism

Distribution Statement : APPROVED FOR PUBLIC RELEASE