Accession Number : ADD017858
Title : Check Bit Code Circuit for Simultaneous Single Bit Error Correction and Burst Error Detection.
Descriptive Note : Patent, Filed 5 Nov 93, patented 10 Oct 95,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Williams, Everett L , III ; Martin, Harold L ; Lo, Jien-Chung
Report Date : 10 Oct 1995
Pagination or Media Count : 17
Abstract : A system for correcting a single bit error and detecting burst errors is provided. A check bit generator generates pantition check bits and burst check bits based on a H-parity matrix data regeneration scheme which provides an a single error correction and multiple bit error detcction code which is linear and has the property of self orthogonality within a subclass of self ortbogonal codes exclusive of Latin square codes. These check bits provide two independent sources for ascertaining the correct value for any given data bit. An error corrector and detector takes as input the data bits and check bits and provides a corrected data bit output as well as a set of error status lines. The error corrector and detector consists of Error Corrector, error corrector/detector and Error Status modules. The Error Corrector and error corrector/detector modules run in parallel providing a high speed Error Correction and Detection implementation, and providing a simplicity of logic structure compatible with application specific integrated circuit (ASIC) design and production processes.
Descriptors : *LOGIC CIRCUITS, *ERROR CORRECTION CODES, *PATENTS, INTEGRATED CIRCUITS, MODULES(ELECTRONICS), PARITY, ORTHOGONALITY, BURST TRANSMISSION
Subject Categories : Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE